Xilinx Vivado : Debugging

HDL instantiation: Full control over all IP core parameters and connections to
signals in the HDL design but can also be difficult to debug a design that is made
up of multiple levels of hierarchy because the signals of interest may need to be
brought to the debug core instance.



CORE insertion: Flexibility to quickly and easily use the debug functionality to an
already synthesized design netlist and to do so without any HDL instantiation.
Most important, the HDL source files will not have to be touched.