FPGA Project Final Year Project

I'm in progress to develop some design, which can be used in Final Year Project in University.


For design service, please contact me by email.


Thanks.

Register Transfer Logic (RTL)

Description of how data is passed from flop to flop and through combinatiorial logic.

Essential FPGA Design (Xilinx Vivado) - 9/4/2013 - 10/4/2013

1) Lab Files: 

Click Here

Note: Password is required to open this lab file.

2) Vivado Impact Tool : How to Program FPGA
Click Here

NCD (Native Circuit Design)

NCD is made after place & route has been successfully completed. It defines the internal logic and interconnections for the FPGA design.

Gigabit Transceiver

In Phy layer
1) PCS (Physical Coding Sublayter) - Performs autonegotiation and coding such as 8b/10b encoding.
2) PMA (Physical Medium Attachment Sublayer) - Perform PMA framing, octet synchronization and detection and scrambling/descrambling.
3) PMD (Physical Medium Dependent Sublayer) This is sublayer consists of a transceiver for the physical medium.

Xilinx Vivado : Debugging

HDL instantiation: Full control over all IP core parameters and connections to
signals in the HDL design but can also be difficult to debug a design that is made
up of multiple levels of hierarchy because the signals of interest may need to be
brought to the debug core instance.



CORE insertion: Flexibility to quickly and easily use the debug functionality to an
already synthesized design netlist and to do so without any HDL instantiation.
Most important, the HDL source files will not have to be touched.

Synthesis Attribute : MARK_DEBUG

MARK_DEBUG is an attribute designated for tagging signals for debug and it is now supported in Vivado IDE design flows. MARK_DEBUG can be applied in multiple ways depending on needs and design flows.

MARK_DEBUG attributes can be applied on on HDL files and synthesized design netlists.